A Primer on Memory Consistency and Cache Coherence

A Primer on Memory Consistency and Cache Coherence

Daniel Sorin, Mark Hill, David Wood
ISBN: 9781608455645 | PDF ISBN: 9781608455652
Copyright © 2011 | 212 Pages | Publication Date: 01/01/2011

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Many modern computer systems and most multicore chips (chip multiprocessors) support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both highlevel concepts as well as specific, concrete examples from real-world systems.

Table of Contents

Introduction to Consistency and Coherence
Coherence Basics
Memory Consistency Motivation and Sequential Consistency
Total Store Order and the x86 Memory Model
Relaxed Memory Consistency
Coherence Protocols
Snooping Coherence Protocols
Directory Coherence Protocols
Advanced Topics in Coherence
Author Biographies

About the Author(s)

Daniel Sorin, Duke University
Daniel J. Sorin is an associate professor of Electrical and Computer Engineering and of Computer Science at Duke University. His research interests are in computer architecture, including dependable architectures, verification-aware processor design, and memory system design. He received a PhD and MS in electrical and computer engineering from the University of Wisconsin, and he received a BSE in electrical engineering from Duke University. He is the recipient of an NSF Career Award and a Warren Faculty Scholarship at Duke. He is the author of a previous Synthesis Lecture, Fault Tolerant Computer Architecture (2009).

Mark Hill, University Wisconsin, Madison
Mark D. Hill is Professor of Computer Sciences and Electrical and Computer Engineering at the University of Wisconsin, Madison. He is the inventor of the widely used 3C model of cache behavior (compulsory, capacity, and conflict misses). He currently co-leads the Wisconsin Multifacet project that develops innovative multiprocessor designs and simulation methods (e.g., GEMS and gem5). He earned a Ph.D. and M.S. from the University of California, Berkeley and a B.S.E. from the University of Michigan, Ann Arbor. Hill is an ACM Fellow, a Fellow of the IEEE, recipient of the ACM SIGARCH Distinguished Service Award, and has won several university awards (Romnes, Vilas Associate, and Kellett). He has had visiting appointments at Sun Microsystems, Universidad Politecnica de Catalunya, Columbia University, AMD, and the University of Washington.

David Wood, University Wisconsin, Madison
Prof. David A. Wood is Professor of Computer Sciences and Electrical and Computer Engineering at the University of Wisconsin, Madison. Dr. Wood has a Ph.D. in Computer Science (1990) from UC Berkeley. Dr. Wood is an ACM Fellow (2006), IEEE Fellow (2004), UW Vilas Associate (2011), UW Romnes Fellow (1999), and NSF PYI (1991). Dr. Wood is Area Editor (Computer Systems) of ACM TOMACS, is Associate Editor of ACM TACO, served as Program Committee Chairman of ASPLOS-X (2002), and has served on numerous program committees. Dr. Wood has published over 80 technical papers and is an inventor on a dozen U.S. and international patents. Dr. Wood co-leads the Wisconsin Multifacet project, which distributes the widely used Wisconsin GEMS full-system multiprocessor simulation system.


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