Die-stacking Architecture

Die-stacking Architecture

Yuan Xie, Jishen Zhao
ISBN: 9781627057653 | PDF ISBN: 9781627057660
Copyright © 2015 | 113 Pages | Publication Date: June, 2015

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The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, promise attractive solutions to reduce the delay of interconnects in future microprocessors. 3D memory stacking enables much higher memory bandwidth for future chip-multiprocessor design, mitigating the "memory wall" problem. In addition, heterogenous integration enabled by 3D technology can also result in innovative designs for future microprocessors. This book first provides a brief introduction to this emerging technology, and then presents a variety of approaches to designing future 3D microprocessor systems, by leveraging the benefits of low latency, high bandwidth, and heterogeneous integration capability which are offered by 3D technology.

Table of Contents

Preface
Acknowledgments
3D Integration Technology
Benefits of 3D Integration
Fine-granularity 3D Processor Design
Coarse-granularity 3D Processor Design
3D GPU Architecture
3D Network-on-Chip
Thermal Analysis and Thermal-aware Design
Cost Analysis for 3D ICs
Conclusion
Bibliography

About the Author(s)

Yuan Xie, University of California, Santa Barbara
Yuan Xie received his B.S. degree in electronic engineering from Tsinghua University, Beijing, in 1997, and his M.S. and Ph.D. degrees in electrical engineering from Princeton University in 1999 and 2002, respectively. He is currently a Professor in the Electrical and Computer Engineering department at the University of California at Santa Barbara. Before joining UCSB in Fall 2014, he was with the Pennsylvania State University from 2003 to 2014, and with IBM Microelectronic Division's Worldwide Design Center from 2002 to 2003. Prof. Xie is a recipient of the National Science Foundation Early Faculty (CAREER) award, the SRC Inventor Recognition Award, IBM Faculty Award, and several Best Paper Award and Best Paper Award Nominations at IEEE/ACM conferences. He has published more than 100 research papers in journals and refereed conference proceedings, in the area of EDA, computer architecture, VLSI circuit designs, and embedded systems. His current research projects include: three-dimensional integrated circuits (3D ICs) design, EDA, and architecture; emerging memory technologies; low power and thermal-aware design; reliable circuits and architectures; and embedded system synthesis. He is currently Associate Editor for ACM Journal of Emerging Technologies in Computing Systems ( JETC), IEEE Transactions on Very Large Scale Integration Systems (TVLSI), IEEE Transactions on Computer Aided Design of Integrated Circuits (TCAD), IEEE Design and Test of Computers, IET Computers and Digital Techniques (IET CDT). He is a Fellow of IEEE.

Jishen Zhao, University of California, Santa Cruz
Jishen Zhao received her B.S. and M.S. degrees from Zhejiang University, and Ph.D. degree from Pennsylvania State University. She is currently an Assistant Professor at the University of California, Santa Cruz. Her research interests include a broad range of computer architecture topics with an emphasis on memory systems, high-performance computing, and energy efficiency. She is also interested in electronic design automation and VLSI design for three-dimensional integrated circuits and nonvolatile memories.

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