On-Chip Photonic Interconnects

On-Chip Photonic Interconnects
A Computer Architect's Perspective

Christopher J. Nitta, Matthew Farrens, Venkatesh Akella
ISBN: 9781627052115 | PDF ISBN: 9781627052122
Copyright © 2013 | 111 Pages | Publication Date: 10/01/2013

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As the number of cores on a chip continues to climb, architects will need to address both bandwidth and power consumption issues related to the interconnection network. Electrical interconnects are not likely to scale well to a large number of processors for energy efficiency reasons, and the problem is compounded by the fact that there is a fixed total power budget for a die, dictated by the amount of heat that can be dissipated without special (and expensive) cooling and packaging techniques. Thus, there is a need to seek alternatives to electrical signaling for on-chip interconnection applications. Photonics, which has a fundamentally different mechanism of signal propagation, offers the potential to not only overcome the drawbacks of electrical signaling, but also enable the architect to build energy efficient, scalable systems. The purpose of this book is to introduce computer architects to the possibilities and challenges of working with photons and designing on-chip photonic interconnection networks.

Table of Contents

List of Figures
List of Tables
List of Acronyms
Acknowledgments
Introduction
Photonic Interconnect Basics
Link Construction
On-Chip Photonic Networks
Challenges
Other Developments
Summary and Conclusion
Bibliography
Authors' Biographies

About the Author(s)

Christopher J. Nitta, University of California, Davis
Christopher Nitta received his Ph.D. in Computer Science from the University of California, Davis and is an adjunct professor of Computer Science at the University of California, Davis. His research interests include network-on-chip technologies, embedded system and RTOS design, and hybrid electric vehicle control.

Matthew Farrens, University of California, Davis
Matthew Farrens received his Ph.D. in Electrical Engineering from the University of Wisconsin and is a professor of Computer Science at the University of California, Davis. His research interests center on computer architecture, with special emphasis on the memory hierarchy. He is a member of ACM and IEEE and a recipient of the NSF PYI award.

Venkatesh Akella, University of California, Davis
Venkatesh Akella received his Ph.D. in Computer Science from University of Utah and is a professor of Electrical & Computer Engineering at University of California, Davis. His current research encompasses various aspects of embedded systems and computer architecture with special emphasis on embedded software, hardware/software codesign and low power system design. He is member of ACM and received the NSF CAREER award.

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