Resilient Architecture Design for Voltage Variation

Resilient Architecture Design for Voltage Variation

Vijay Janapa Reddi, Meeta Sharma Gupta
ISBN: 9781608456376 | PDF ISBN: 9781608456383
Copyright © 2013 | 138 Pages | Publication Date: 05/01/2013

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Shrinking feature size and diminishing supply voltage are making circuits sensitive to supply voltage fluctuations within the microprocessor, caused by normal workload activity changes. If left unattended, voltage fluctuations can lead to timing violations or even transistor lifetime issues that degrade processor robustness. Mechanisms that learn to tolerate, avoid, and eliminate voltage fluctuations based on program and microarchitectural events can help steer the processor clear of danger, thus enabling tighter voltage margins that improve performance or lower power consumption. We describe the problem of voltage variation and the factors that influence this variation during processor design and operation. We also describe a variety of runtime hardware and software mitigation techniques that either tolerate, avoid, and/or eliminate voltage violations. We hope processor architects will find the information useful since tolerance, avoidance, and elimination are generalizable constructs that can serve as a basis for addressing other reliability challenges as well.

Table of Contents

Introduction
Modeling Voltage Variation
Understanding the Characteristics of Voltage Variation
Traditional Solutions and Emerging Solution Forecast
Allowing and Tolerating Voltage Emergencies
Predicting and Avoiding Voltage Emergencies
Eliminiating Recurring Voltage Emergencies
Future Directions on Resiliency

About the Author(s)

Vijay Janapa Reddi, The University of Texas at Austin
Vijay Janapa Reddi is an Assistant Professor in the Department of Electrical and Computer Engineering at The University of Texas in Austin. His research interests are in the area of computer systems,focusing on the interactions between hardware and software.He explores new opportunities and synergies for cross-layer solutions that improve processor- and system-level power, performance and reliability.He has co-authored over 30 papers in these areas, and has papers selected as IEEE Micro Top Picks and received Best Paper Awards. Dr. Janapa Reddi has also worked in the computer industry, specifically focusing on processor architecture and compiler aspects at companies such as Intel, VMware, AMD Research, and Microsoft Research. One of his most significant contributions to the community is the Pin dynamic compiler that he co-authored on a 4-year stint at Intel. Pin is widely used in academia and industry for program introspection and analysis. Dr. Janapa Reddi received his Ph.D. in Computer Science from Harvard University. He has a M.S. degree from the Department of Electrical and Computer Engineering at the University of Colorado at Boulder.His B.S.degree is from the Computer Engineering department at Santa Clara University.

Meeta Sharma Gupta, IBM T.J. Watson Research
Meeta S. Gupta is a Research Staff Member in the Reliability and Power-Aware Microarchitecture department at IBM T. J. Watson Research Center. Her research interests include high-performance computing, reliability, and power-aware computer architecture design.Dr.Gupta is involved in general areas of processor reliability, inductive noise, and Exascale systems. Microarchitectural techniques for reliability enhancement have also been part of her research focus. Dr. Gupta received her Ph.D. degree in Electrical and Computer Engineering from Harvard University. She received a Master's in EE from the University of Southern California, Los Angeles, and a Bachelor's degree in Electrical Engineering from the Indian Institute of Technology, Delhi. Dr. Gupta also held positions in Advanced Mobile Networking Group at Lucent Bell Labs and in the High-Performance Computing group at IBM India Research Labs, Delhi. Dr. Gupta was the recipient of the IBM Ph.D. Fellowship.

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