Computer Architecture

SERIES EDITOR:
Margaret Martonosi, Princeton University
FOUNDING EDITOR EMERITUS: Mark D. Hill, University of Wisconsin-Madison
This series covers topics pertaining to the science and art of designing, analyzing, selecting and interconnecting hardware components to create computers that meet functional, performance and cost goals. The scope will largely follow the purview of premier computer architecture conferences, such as ISCA, HPCA, MICRO, and ASPLOS.

Series ISSNs: 1935-3235 (print) and 1935-3243 (electronic)

Editor Bios


Phase Change Memory Phase Change Memory
Moinuddin K. Qureshi, Sudhanva Gurumurthi, Bipin Rajendran
As conventional memory technologies such as DRAM and Flash run into scaling challenges, architects and system designers are forced to look at alternative technologies for building future computer systems. This synthesis lecture begins by listing the ...
Publication Date: 01/01/2011

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Performance Analysis and Tuning for General Purpose Graphics Processing Units (GPGPU) Performance Analysis and Tuning for General Purpose Graphics Processing Units (GPGPU)
Hyesoon Kim, Richard Vuduc, Sara Baghsorkhi, Jee Choi, Wen-mei W. Hwu
General-purpose graphics processing units (GPGPU) have emerged as an important class of shared memory parallel processing architectures, with widespread deployment in every computer class from high-end supercomputers to embedded mobile platforms. Rel...
Publication Date: 01/01/2012

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Multithreading Architecture Multithreading Architecture
Mario Nemirovsky, Dean Tullsen
Multithreaded architectures now appear across the entire range of computing devices, from the highest-performing general purpose devices to low-end embedded processors. Multithreading enables a processor core to more effectively utilize its computati...
Publication Date: 01/01/2013

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Multi-Core Cache Hierarchies Multi-Core Cache Hierarchies
Rajeev Balasubramonian, Norman P. Jouppi, Naveen Muralimanohar
A key determinant of overall system performance and power dissipation is the cache hierarchy since access to off-chip memory consumes many more cycles and energy than on-chip accesses. In addition, multi-core processors are expected to place ever hig...
Publication Date: 01/01/2011

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Automatic Parallelization Automatic Parallelization
Samuel Midkiff,
Compiling for parallelism is a longstanding topic of compiler research. This book describes the fundamental principles of compiling "regular" numerical programs for parallelism. We begin with an explanation of analyses that allow a compiler to unders...
Publication Date: 01/01/2012

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Transactional Memory, Second Edition Transactional Memory, Second Edition
Tim Harris, James Larus, Ravi Rajwar
The advent of multicore processors has renewed interest in the idea of incorporating transactions into the programming model used to write parallel programs. This approach, known as transactional memory, offers an alternative, and hopefully better, w...
Publication Date: 01/01/2010

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Quantum Computing for Computer Architects, Second Edition Quantum Computing for Computer Architects, Second Edition
Tzvetan Metodi, Arvin I. Faruque, Frederic T. Chong
Quantum computers can (in theory) solve certain problems far faster than a classical computer running any known classical algorithm. While existing technologies for building quantum computers are in their infancy, it is not too early to consider thei...
Publication Date: 01/01/2011

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Processor Microarchitecture Processor Microarchitecture
Antonio Gonzalez, Fernando Latorre, Grigorios Magklis
This lecture presents a study of the microarchitecture of contemporary microprocessors. The focus is on implementation aspects, with discussions on their implications in terms of performance, power, and cost of state-of-the-art designs. The lecture s...
Publication Date: 01/01/2010

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Introduction to Reconfigurable Supercomputing Introduction to Reconfigurable Supercomputing
Marco Lanzagorta, Stephen Bique, Robert Rosenberg
This book covers technologies, applications, tools, languages, procedures, advantages, and disadvantages of reconfigurable supercomputing using Field Programmable Gate Arrays (FPGAs). The target audience is the community of users of High Performance ...
Publication Date: 01/01/2009

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High Performance Datacenter Networks High Performance Datacenter Networks
Dennis Abts, John Kim
Datacenter networks provide the communication substrate for large parallel computer systems that form the ecosystem for high performance computing (HPC) systems and modern Internet applications. The design of new datacenter networks is motivated by a...
Publication Date: 01/01/2011

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Dynamic Binary Modification Dynamic Binary Modification
Kim Hazelwood
Dynamic binary modification tools form a software layer between a running application and the underlying operating system, providing the powerful opportunity to inspect and potentially modify every user-level guest application instruction that execut...
Publication Date: 01/01/2011

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Computer Architecture Performance Evaluation Methods Computer Architecture Performance Evaluation Methods
Lieven Eeckhout
Performance evaluation is at the foundation of computer architecture research and development. Contemporary microprocessors are so complex that architects cannot design systems based on intuition and simple models only. Adequate performance evaluatio...
Publication Date: 01/01/2010

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A Primer on Memory Consistency and Cache Coherence A Primer on Memory Consistency and Cache Coherence
Daniel Sorin, Mark Hill, David Wood
Many modern computer systems and most multicore chips (chip multiprocessors) support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, t...
Publication Date: 01/01/2011

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The Memory System The Memory System
Bruce Jacob
Today, computer-system optimization, at both the hardware and software levels, must consider the details of the memory system in its analysis; failing to do so yields systems that are increasingly inefficient as those systems become more complex. Thi...
Publication Date: 01/01/2009

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Fault Tolerant Computer Architecture Fault Tolerant Computer Architecture
Daniel Sorin
For many years, most computer architects have pursued one primary goal: performance. Architects have translated the ever-increasing abundance of ever-faster transistors provided by Moore's law into remarkable increases in performance. Recently, howev...
Publication Date: 01/01/2009

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Computer Architecture Techniques for Power-Efficiency Computer Architecture Techniques for Power-Efficiency
Stefanos Kaxiras, Margaret Martonosi
In the last few years, power dissipation has become an important design constraint, on par with performance, in the design of new computer systems. Whereas in the past, the primary job of the computer architect was to translate improvements in operat...
Publication Date: 01/01/2008

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Chip Multiprocessor Architecture Chip Multiprocessor Architecture
Kunle Olukotun, Lance Hammond, James Laudon
Chip multiprocessors - also called multi-core microprocessors or CMPs for short - are now the only way to build high-performance microprocessors, for a variety of reasons. Large uniprocessors are no longer scaling in performance, because it is only p...
Publication Date: 06/01/2007

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